SK Hynix revealed more details about its upcoming DDR5-6400 memory chip at International
The 16 Gb DDR5 memory chip is arranged in 32 banks and 8 bank groups with a 6400 MT/s interface transfer rate at 1.1 Volts. SK Hynix is using its second generation 10nm-class fabrication technology (also known as 1y nm tech) for the fabrication of this device with four metal layers and a die size of 76.22mm2.
SK Hynix’s 8 Gb DDR4 DRAM, which is fabricated on its first generation 21 nm manufacturing process has a die size of 76mm2, while a similar DDR5 device made using the second generation 21nm manufacturing process has a die size of 53.6 mm2. Although a die size of 76mm2 can be considered to be quite high, the company has made great efforts in improving its DRAM density per square millimeter. This is good news for the consumers as it’ll allow them to produce cost-effective 8 Gb DDR5 chips.
DDR5 DRAM obviously provides better performance than DDR4 along with higher per-chip capacities. This upgrade in performance means working at higher frequencies. High frequencies sometimes lead to issues like clock jitter and clock duty cycle distortion and in order to reduce these, SK Hynix implemented a new delay-locked loop (DLL) using a phase rotator and an injection locked oscillator. Additionally, the chip also has a revised forward feedback equalization (FFE) circuit, and a new write-level training method to allow for higher frequency operation.
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