NVIDIA Ampere Architecture Will Use TSMC’s 7nm Process or Even 6nm


    Unrest is brewing in both the CPU and GPU markets. Starting with AMD’s Ryzen 3000 series on one side and Intel’s discrete Xe graphics on the other, the next 12-24 months might change the entire landscape of the desktop microprocessor industry. AMD is the first of the big three to fully migrate to the 7nm node, while Intel is still stuck on its 14nm process, and NVIDIA doesn’t have any reason to rush things. However, it’s very much possible that team green might leap-frog Lisa Su and Co, by directly adopting TSMC’s 6nm node that has just been revealed.

    TSMC 7nm Chip NVIDIA Ampere

    TSMC has unveiled its new 6nm manufacturing process, which will succeed the company’s present flagship 7nm node. The 6nm node or N6 as its called will have the same basic design as its predecessor but will be 18% denser, without increasing the TDP or compromising performance.

    From what TSMC has shared till now, N6 (or the 6nm process) will basically be an extension of the present N7 (or 7nm) with the same EUV benefits as 7nm+. Chip architects won’t have to re-create the entire design to move to N6, instead, the older 7nm ones should do just fine. This will result in 15% smaller die sizes with the same performance and power requirements.


    AMD Zen3 Based CPUs to Make Use of 7nm EUV Process

    NVIDIA Ampere 7nm Process

    TSMC is said to start risk-production of the 6nm chips in the first quarter of 2020. It usually takes a year for this phase to end, but in case you haven’t forgotten, the company recently started risk-production of the 5nm process as well. That means by mid-2020 those chips should be good for production.

    This is mere speculation at this point, but one thing is for sure. The next round of the battle will be fought using the 7nm process at the very least. NVIDIA generally tends to be the last one to migrate to the next process, but its Ampere architecture will most certainly not use the present 12nm node. It’ll either be N7 or N6, with a possibility that N5 (5nm) might also be utilized although I think that’s highly unlikely.

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