Right alongside Apple’s new MacBook Pro announcement, Intel announced it’s Xeon W CPUs ranging from octa-core to 24 core parts, all hyper-threaded. Unlike their predecessors, the newer Xeon W lineup ditches the FCLGA-2066 packaging in favor of the FCLGA-3647 package.

To make up for the lack of architectural updates, Intel has essentially doubled the core count of the Cascade Lake workstation chips. Furthermore, unlike Skylake which has a total of 14 CPUs, the newer generation consists of just 9, out of which three are just beefed up M variants with support for up to 2 TiB memory. The remaining six have support for hex-channel DDR4-2933 memory (up to 1 TiB). These chips leverage the same instruction set as the preceding W-2100 series, namely AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX-512-F/CD/BW/DQ/VL/VNNI with 2 FMA units).

Cascade Lake Xeon W
Source: WikiChip

The increase in core count can be primarily seen as a last resort against AMD’s Zen 2 onslaught, as the company is expected to launch the Threadripper 3 chips soon, and the 64-core Epyc Rome has caused Intel enough grief as it is.

This becomes even more apparent if you consider the upgrades over the Skylake processors. Other than the core count, the Xeon 2 3200 lineup also has an increased PCIe lane count, a total of 64, x16 more than its predecessors. This is the highest PCIe lanes any Intel chip has ever had. The TR’s 60 PCIe lanes are probably what prompted this decision. However, these are still based on the third-gen PCIe standard while the Zen 2 chips come with PCIe 4.0 support.

Cascade Lake Xeon W

Another less prominent improvement is the addition of Turbo Boost Max 3.0. This allows the Cascade Lake CPUs to run the “superior cores” at higher frequencies. Ironically, these processors don’t seem to have support for Intel’s Optane DC Persistent Memory which has been one of the most advertised features of the Server-class Cascade Lake lineup.

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