It is no secret that Intel’s Tick-Tock model is a thing of the past. The company officially adopted the “Process-Architecture-Optimization model” in 2016, but to be fair that
Intel already seems to be investing heavily in this field with Foveros and EMIB (Embedded Multi-die Interconnect Bridge), the former ready to debut with the Lakefield SoC next year while the latter was unveiled back in 2017. EMIB was first seen on the Kaby Lake-G chip that incorporated AMD’s Radeon Vega graphics with 4GB of HMB2 memory and will continue to be featured in core designs in the coming years as well. Foveros is a 3D die-stacking technology that will be first leveraged by the Lakefield SoC followed by industry-wide adoption to realize heterogeneous integration. This basically involves packing together individually manufactured silicon and non-silicon components into 3D SiP (System-in-Package).
As for Intel’s “process technologies”, 10nm finally seems to have been shipped with the first Icelake devices expected in late 2019 in the form of the mobile (U) chips. The desktop and server parts will roll out in 2020, followed by an architectural refresh later that year (probably). The 7nm node will initially be used by the Xe discrete graphics processors, the first wave slated for release in 2020 (10nm for Gen1) while the CPUs will make the jump in 2021, followed by 7nm+ and 7nm++ in the next consecutive years.
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