Earlier this week, details about the EPYC Milan and Genoa processors were leaked. EPYC Milan will be based on the AMD Zen 3 microarchitecture while the Genoa series will be based on Zen 4. Surprisingly, the actual SoC design was also leaked which gives us a pretty decent idea regarding the Zen 3 microarchitecture.
Similar to the EPYC Rome series of server chips, Milan will feature 64C/128T embedded across eight 8-core chips. In the first Zen design, groups of cores (called CPU Complex) consisted of 4 cores connected to an L3 cache. Every core has access to the L3 cache without any major difference in latency. There may be more than one CCX module attached depending on the type of processor. For example, the mainstream Ryzen processors have 2 CCX joined together (with 8 cores in total) while the Threadripper processors have 4 CCX (for a total of 16 Cores).
AMD is looking to move from this 1st generation Zen design as the Milan processors will feature a unified 32 MB of L3 cache. With Zen 2, AMD relocated the I/O controller die on the processor, away from the CPU chiplet. This proves that AMD is looking to slowly move away from the CCX arrangement with AMD Zen 3. Milan will also feature an updated SMT technology that will further double the number of logical processors per core. It will also retain support for PCIe 4.0 and DDR 4 memory.
While the upcoming EPYC Milan launch might not look so gorgeous on paper, it will herald the way for an updated SoC architecture. Moreover, the EPYC Genoa processors scheduled to release in 2021 will introduce the SP5 socket. It will also include support for PCIe 5.0 and DDR5 memory.