AMD Set to Utilize TSMC 5nm Node For Zen 3 Based Ryzen 4000 Series

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    AMD’s new Zen 2 architecture based next-gen desktops performed well at the market and proved to be significantly superior to its predecessor. Recently Digitimes has reported major information regarding the Zen 3 series. Reportedly, AMD would be dropping the TSMC’s 7nm EUV process and replace it with a 5nm node for its new Zen 3 architecture. The computer-giant would use the Zen 3 in its upcoming Ryzen 4000 Desktop series codenamed ‘Vermeer‘.

    Ryzen 4000 Set to Utilize 5nm+ Process Node

    The report which was shared by Chia at Twitter suggests that AMD would be one of the leading customers of the TSMC 5nm+ process node. It was speculated that AMD would replace its current Zen 2 which features TSMC’s 7nm node with a more advanced 7nm EUV process for its Zen 3. However, it appears as if the tech giant has decided to go for the new high-tech 5nm+ process node. This would give then Zen 3 processors a huge performance uplift over the current Zen 2 processors. The report suggests that AMD would be the first to use the new 5nm+ process node in its new Zen 3 line-up.

    Since TSMC has announced the mass production of the chip in the fourth quarter of 2020, we can expect the availability and launch to take place by 2021. The CES 2021 can be a launch platform for the unveiling of the next-gen Ryzen 4000 ‘Vermeer’ series. However, the reports only mention Ryzen 4000 series to use a 5nm+ process node. The Milan lineup of EPYC CPU’s are also going to use the new Zen 3 architecture, however, it is not mentioned in the report. It is suspected that AMD would delay the first server shipment to 2021 to use the new 5nm+ process node in them too.

    The report suggests that AMD is not just going for the 5nm node process for Ryzen 4000 but a much-advanced version of it. It was reported previously that the Zen 4 architecture would feature the new 5nm+ node process. However, it appears that AMD went ahead to step up the competition and used this exclusive processor for Zen 3 architecture.

    Zen 3 (Ryzen 4000) ‘Vermeer’ CPUs

    The upcoming new Zen 3 architecture is expected to be the greatest CPU design since the original Zen. The upcoming chip has been completely revamped and focuses on three main features which include IPC gains, faster clock speeds, and high efficiency. Some rumors point out that the new Zen architecture brings 17% IPC gains along with a 50% increase in the floating-point operations in Zen 3 along with major cache redesign. The EPYC presentation highlighted that the new upcoming architecture would be having a unified cache. This would double the cache each Zen 3 core has access to compared to the Zen 2.

    The new CPU’s are also expected to get a 200-300 MHz clock boost. This would bring the Zen 3 Ryzen processors close to Intel’s 9th Generation Core Offering. The massive clock boost along with the significant IPC gain and come general architecture changes would result in a much faster performance over Ryzen 3000 which was already a massive improvement over Ryzen 2000 and Ryzen 1000 series.

    What Could This Mean for the Market?

    The new Zen 3 processor would featuring a 5nm+ node process set to be with the 2021 line-up of AMD could be a serious blow to Intel. The reason being that Intel would still be relying on the TSMC 10nm process for the majority of their 2021 line-ups. The Ryzen ‘Vermeer’ line-up would be competing against Intel’s upcoming Comet Lake-S and Rocket Lake-S desktop processors. The Ryzen 3000 is already a competitor to Intel’s Comet Lake-S according to various recent performance leaks. However, Rocket Lake-S is a bigger uplift for Intel. But the Intel’s Rocket Lake-S still needs to evaluate before being called a competitor for Zen 3.

    At this point of time all these reports are not officially confirmed so nothing is set in stone yet. However, if the new Rocket Lake-S proves to be a competitor over Zen 3 even then AMD would be at an advantage because of the availability of the new 5nm+ node process technology.

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