If you have been keeping tabs on the CPU industry, then you probably remember Intel’s recently announced Lakefield SoC. The chip brings a slew of new technologies, including stacked DRAM, different core clusters as well as the 10nm node (probably). At the time, AMD didn’t quite have anything to counter team blue’s latest challenge. Well, that’s no longer the case. AMD yesterday confirmed that it is working on Foveros-like designs to leverage stacked 3D DRAM and SRAM to improve the performance and efficiency of its future chips.
As Moore’s law dies a slow death and frequencies start hitting the ceiling, all major players in the Silicon Valley are looking towards alternatives to keep the momentum going. One of these include 3D stacked memory. NVIDIA had earlier mentioned it, but that didn’t quite pan out, Intel recently demonstrated it with the Lakefield SoC and AMD has already done it with HBM2 memory on its Vega cards. Forrest Norrod, the company’s SVP and GM at a recent HPC conference shared that team red is developing its own 3D stacking technology for future processors. It’s unlikely that the Zen2 based Ryzen 3000 chips will leverage 3D memory, but its successors should use it.
Norrod said what everyone already knows that die-shrinking is getting harder and harder and clock speeds aren’t increasing at the anticipated rates, so just like Intel and NVIDIA, AMD is also looking towards unconventional solutions such as 3D die stacking.
The dirty little secret in the industry, though, over the last ten years that has stopped, and may now be regressing[…]As we continually shrink our processes now, we don’t get any more frequency, and really with this next node, without doing extraordinary things, we get less frequency.
Forrest Norrod
AMD’s stacked memory approach is going to differ from the orthodox package-on-package (PoP) implementation. In AMD’s case, the DRAM package is connected through additional rows of BGA connectors that control the flow of data between the two chips (instead of being connected directly). The PoP technique increases the density by a lot, but when it comes to sheer performance it leaves a lot to be desired.
The TSV connections used in PoP implementations have the highest possible data transfer rates between the two dies, and they also increase the chip density and bring down the TDP.
Both Intel and AMD have revealed just the basics of the still-under-development 3D stacked memory architectures, but it sure is going to be one of the most prominent advancements in the microprocessor space we’ve seen in a while.
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