It appears that the Zen 2 based 7nm iteration of the Ryzen APUs will be coming soon. According to a report from WCCFTech, AMD will be releasing the Renoir APUs by the end of this year. Now before I proceed, let me point this out. The outlet calls it the “Raven Ridge refresh”, but it wouldn’t make much sense to backtrack to the 14nm Raven Ridge design after Picasso now that Zen 2 is out and doing really well too.
If WCCFT isn’t wrong then the Zen 2 based “Renoir” APUs will launch in the last quarter of this year, a few months after the Navi launch. So, as the Radeon RX 5700 graphics cards are launching in July, we are looking at a November or December release window.
A Zen 2 based quad-core Ryzen APU paired with a Vega GPU (Navi maybe?) will pack enough oomph to satisfy most users’ basic needs, from casual gaming to word-processing, and as long as you’re not building a gaming rig, there’s very little reason to opt for an additional discrete GPU.
As for the core and cache configurations, since the 3rd Gen Ryzen lineup isn’t all that different from the preceding Zen+ CPUs, I don’t think things will change much on the APU side either. We’ll probably get higher clock speeds, along with increased cache sizes but the core and thread counts should more or less stay unchanged. The GPU shouldn’t be all that different either. I expect the same Vega parts with higher clocks thanks to the 7nm node.
The new Zen 2 APUs should perform on par with the lower end i5s such as the Intel Core i5-9400, with better multi-threaded performance in certain scenarios. Given past tradition,
I expect Renoir to be Vega graphics based. I think Navi implementation might be waiting for DDR5 and a new socket (AM5?). 11 CU Vega is memory bandwidth limited. APU is always a low-cost option so won’t lead the new memory and socket implementation. It makes sense to implement a new APU arch when all the pieces are in place for a significant leap in performance so it can be long lived and a comercial success dispite low margins. Navi on its own would still be memory bound and not much improvement but Navi (with its more efficient use of memory) + DDR5 (doubling memory bandwidth) would be something. Would this allow 20+ CU’s? Die size and cost could become a limiting factor. I expect it would be implemented on a mature process node like the APU’s proceding it. Navi with higher IPC plus higher clocks might not need that many CU’s to double iGPU performance.